In standard CMOS devices, polysilicon is typically the standard gate material. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. One advantage of using polysilicon gates is that such silicon-based gates can sustain high temperatures. However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect and relative high electrical sheet resistance, polySi gates commonly used in CMOS devices are becoming a gating factor in chip performance for channel lengths of 0.1 micron and below. Another problem with polySi gates is that the dopant in the polySi gate, such as boron, can easily diffuse through the thin gate dielectric causing further degradation of the device performance.
In order to avoid the problems with polySi gates, it has been suggested to replace the polySi gate with a single metal. Although such technology has been suggested, single metals on a high-k (dielectric constant greater than about 4.0) layer have two important reliability issues that need to be considered. One of the reliability issues associated with a gate stack including a metal gate and a high-k gate dielectric is that of charge trapping induced threshold voltage (Vt) shifts. Another reliability issue of concern in such metal-containing gate stacks is gate leakage current degradation under prolonged electrical stressing.
Both charge trapping and gate leakage degradation impact the long term stability of the device and need to be reduced for the successful implementation of high-k/metal gate stacks in CMOS technology.
In view of the above, there is a need for providing a gate stack including a metal gate located on a high-k gate dielectric in which charge trapping and gate leakage degradation have been reduced.